1. Field of the Invention
The present invention relates to the field of wireless communication.
2. Prior Art
Zero-IF receivers for wireless communication use AC coupling in the I and Q base band signal paths to block the unwanted DC levels due to local oscillator (LO) leakage and circuit implementation. After adjusting the receiver gain, the AC coupling is switched to DC coupling in order to improve the signal to noise ratio (S/N). In doing this, a large DC step may be observed in the I and Q signal paths due to the series capacitor retaining some signal dependent charge existing at the moment of switching. This can result in clipping of the I and Q A/D inputs and also in impairment of the S/N.
A prior art circuit for DC cancellation is shown in FIG. 1a. VDC is the unwanted DC offset that is blocked by C1 when the switch S1 is in the AC position. The R1C1 time constant implements a high-pass filter (AC coupling) with a 3 dB corner frequency
      f    HP    =            1              2        ⁢        π        ⁢                                  ⁢                  R          1                ⁢                  C          1                      .  If the wanted signal has a frequency component VAC at a much lower frequency f1<<fHP, then C1 will charge up close to the instantaneous value of that frequency component in VAC and the AC voltage across C1, i.e., VC1AC, will follow that frequency component in VAC. When the switch S1 is opened (DC position) for implementing DC coupling, the instantaneous voltage across C1 will be VDC+VC1AC (t=0), assuming the switching is done at time t=0. The VDC component of voltage across the capacitor C1 is the desired blocking of the unwanted DC offsets. However the output VOUT will now have a DC kick equal to VC1AC (t=0), which in the worst case will be nearly as large as the amplitude of VAC at f1.
The applicable waveforms are shown in FIGS. 1b through 1f FIG. 1b shows the wanted input signal VAC, FIG. 1c a representative DC offset level VDC, and FIG. 1d, the input voltage VIN to the high pass filter (R1,C1), which is the sum of the wanted input signal VAC and the representative DC offset level VDC. Assuming the wanted signal VIN is at a frequency of f1<<fHP, the voltage VC1ac across the capacitor C1 prior to switching switch S1 (FIG. 1a) to the DC position will substantially follow the wanted signal VIN, as shown in FIG. 1e. At the moment of switching (t=0), that signal may have an amplitude anywhere within its maximum amplitude. FIG. 1e illustrates an arbitrary value at the time of switching that is Vstep above the VDC level. This unwanted DC step of Vstep=VC1AC (t=0) then is coupled to the next functional element in the signal path, as shown in FIG. 1f. 